This invention relates to a method of producing an LSI chip by which the process of forming bumps is significantly simplified and the cost of such a process can be reduced, and an LSI chip produced by such a method.
Conventional methods of forming an LSI chip on a substrate can be roughly divided into the following categories: wire bonding methods whereby the LSI chip is directly mounted on a substrate by wiring, and TAB (tape automated bonding) or flip chip bonding methods whereby the LSI chip is mounted on a substrate after a protrusions referred to as bumps are initially produced on the chip. These methods will be described below individually together with their characteristics and disadvantages.
(i) Wire Bonding Methods
By a wire bonding method, a gold wire, an aluminum wire or the like is used to mount the LSI chip. An example of LSI chip mounted on a lead frame is shown in FIG. 16 wherein numerals 1, 2, 3 and 4 indicate an LSI chip, a lead frame, a looping wire and a package, respectively. After the mounting, a plastic resin or ceramic material may be used for sealing and products thus obtained may be referred to as DIP (dual inline package), QFP (quarter flat package) or CC (chip carrier) and they are mounted on a substrate by soldering, etc. In other words, the LSI chip 1 is wire-bonded first to the lead frame 2 (inner bonding) and this lead frame 2 is then soldered (outer bonding) to a wiring substrate. This method is advantageous from the point of view of cost because there is no processing to be performed on the LSI chip. In the case of a multi-pin LSI chip, however, its external size becomes much greater than the size of the LSI chip itself because outer bonding must be performed and a large area is required for its mounting as illustrated in FIG. 17 wherein the same numerals as in FIG. 16 are used to indicate the same or equivalent components. In summary, the wire bonding methods are disadvantageous where high-density mounting is required. In order to eliminate this disadvantage, so-called COB (chip on board) methods are currently developed whereby the LSI chip is directly connected to the substrate by wiring but the thickness of Au
solder on the board for wiring is required to be 2-3 .mu.m, or 20-30 times as large as in the case of an ordinary board for soldering and this increases the cost of the board. As described above, furthermore, the wire 3 in a wire bonding method must be looped and this has the unfavorable consequence of increasing the thickness of the package considerably over that of the LSI chip 1 itself. Thus, this method is not suitable for thin products.
(ii) TAB Methods
With reference to FIG. 18 which shows an example of this method, numeral 5 indicates an LSI chip preliminarily provided with Au bumps 6 and when this LSI chip 5 is mounted, the bumps 6 are bonded to an Au-plated or Sn-plated lead wire 8 of a film carrier 7 having a polyimide or glass epoxy film as base. After the mounting, the device molded by a resin material 9 is inspected, separated from the film base and attached to a board by plating or conductive bonding (outer bonding). One of the advantageous characteristics of this method is that it can be used for effecting thin mounting. According to a recently developed method of using an anisotropic conductive adhesive for outer bonding, connections with a fine pitch not possible by a conventional soldering method can be achieved such that multi-pin LSI chips with as many as about loop pins can be formed effectively. This method is disadvantageous, however, in that Au bumps 6 must be formed first on the LSI chip 5 and that the photo-process as well as the vapor deposition, plating and etching processes must be repeated in the form of the wafer. Moreover, the cost of the LSI becomes high because of these processes. Although a method of transferring Au bumps to an LSI chip has recently been developed and this method is advantageous in that the LSI can be handled in the form of a chip, the transferred bumps themselves still require the photo-process and the vapor deposition, plating and etching processes and there is the extra process of transferring the bumps. In other words, this method is still disadvantageous because of the increased cost of transferred bumps and the increased number of processes.
(iii) Flip Chip Bonding Method
This method is frequently used as shown in FIGS. 19 and 20 when bumps 11 of a Pb-Sn alloy are first formed on an LSI chip 10 and it is mounted directly on a board. One of the characteristics of this method is that connection can be made to a wire 13 on the wiring board 12 directly below the LSI chip 10 since bumps 11 can be provided by effectively using the surface of the LSI chip 10 and that there is no need for Al wiring inside the LSI. Numeral 14 in FIG. 19 indicates a mold material. Accordingly, the action becomes faster and the device size can be reduced since there is no need to extend electrodes through the neighborhood of the LSI chip by this method unlike the wire bonding or TAB method. As in the TAB method, however, the process of forming the Pb-Sn bumps 11 by this method is complicated and the cost of LSI becomes high. Moreover, since the device is inspected only after the mounting is completed on the board, defects cannot be corrected in the mounted condition.